This invention relates to a memory device and, more, particularly, to a function test for an error-detection/correction means provided in the memory device.
In a memory device, that is, specifically, an EEPROM, there is a possibility that data previously stored in a memory cell array may be affected and changed by writing or reading data into or from a memory area in the vicinity of that previously stored data. For this reason, the memory device is usually provided with a means for detecting and correcting errors in data stored in the memory device. For example, this means operates so that when data are written in a memory cell array, an error check code (hereinafter referred to as "ECC") is formed with respect to each data item. This error check code is written, together with the corresponding data item, into an assigned address in the memory cell array. If if the data is thereafter read out, detection and correction of errors in the data is performed with respect to each read data item by using the ECCs formed at the time of writing. Examples of this type of memory device are disclosed in Japanese Patent Publication Nos. 62-32822 and 62-32823. The system disclosed in Japanese Patent Publication No. 62-32823 detects and corrects data errors by storing 8-bit data with a 4-bit ECC attached. FIG. 2 is a block diagram in which the construction of a conventional memory device such as that disclosed in Japanese Patent Publication No. 62-32822 for detecting and correcting data errors is schematically illustrated. As shown in FIG. 2, a memory device 10 (e.g., an EEPROM) connected between data buses 21a and 21b is constituted by an internal ECC formation circuit 11, a memory cell array 12 and an error-detection/correction circuit 13. A processor (not shown) controls writing and reading operations. If, at the time of writing, data is supplied from the processor to the memory cell array 12 via the input-side data bus 12a and a data signal line D, the internal ECC formation circuit 11 forms an internal ECC for the data and stores this code in an assigned address of the memory cell array 12 via an ECC signal line E. At the time of reading, the data and the corresponding internal ECC are read from the assigned addresses of the memory cell array 12, and the error-detection/correction circuit 13 detects and corrects errors in the data using the internal ECC and thereafter supplies the data to the output-side data bus 21b. There are various methods of performing error checking in this system. For example, the error-detection/correction circuit 13 may calculate, at the time of reading, an ECC with respect to the read data in the same manner as in the case of ECC formation at the time of writing and compare this ECC with the internal ECC formed in the internal ECC formation circuit 11 at the time of writing. An error in the data may be detected from the comparison and thereafter corrected. This method is disclosed in Japanese Patent Publication No. 62-32825.
Conventionally, a function test for the errordetection/correction circuit 13 is usually performed in the following manner. As indicated by the broken line in FIG. 2, a change-over switch 14 and a register 15 for receiving and storing an ECC set from the outside (hereinafter referred to as "external ECC register") are provided, and the external ECC register 15 is selectively connected to the memory cell array 12. To perform a function test, the connected switch 14 is changed over to the external ECC register 15, and a desired external ECC for function testing, the content of which is known . The content of the external ECC is written into the register 15, for example, from the processor (not shown). At the same time, data for function testing, the content of which is known (e. g., all "0" data such as 00000000 if the data is 8-bit data), is input via the data signal line D. The ECC and the data thereby supplied are temporarily stored, in combination with each other, in the memory cell array 12. The data thereby stored are read out and tested to determine whether or not the read data is suitably corrected in the error-detection/correction circuit 13 on the basis of the external ECC before it is supplied to the output-side data bus 21b.
To perform the function test for the errordetection/correction circuit in the thus-constructed memory device, the data and an ECC set from the outside for function testing, the contents of which are known, must be temporarily stored in the memory cell array. For this reason, the test process is time-consuming and troublesome. There is also the problem that in a defect of the memory cell array can influence the test results since, in this test, the data and the ECC are temporarily stored in the memory cell array.